Inside LPULite

Electricity is electrons that are free to move

1. An atom: a positive nucleus (+) with negative electrons (−) around it. Opposite charges attract.
2. In copper the outermost electron is barely held. It leaves its atom and roams: a sea of free electrons, jiggling randomly.
3. In glass every electron is bound to its own atom. It can wobble, it cannot travel. That is an insulator.
4. Back to copper. Press push: the whole sea drifts one way. Moving charge is a current.
5. The gate on the right counts electrons crossing. 6.24×10¹⁸ of them per second is 1 ampere (1 coulomb per second).

Voltage is a push, measured from a reference

1. A raised tank pushes water down a pipe. Higher tank → harder push (pressure).
2. The circuit on the right is the same picture: a supply lifts charge up, it flows down through a load (a lamp).
3. The bottom wire is ground = 0 V: the floor every other voltage is measured from.
4. The top wire is the supply rail, VDD. Every point in between sits at some height between 0 and VDD.
5. Drag the slider: raise VDD and both the water and the charge are pushed harder. At 0 V: no push, nothing flows.

Current flows one way on paper and the other way in the wire

1. Current = charge passing the dashed cut each second. Measured in amperes (A).
2. The conventional arrow (blue) goes from + to − outside the battery. All schematics use this.
3. But electrons are negative, so they really move − to + (yellow dots). Same current, opposite labels.
4. Close the switch: the push (yellow front) races around the loop and the lamp lights almost at once.
5. Watch the red tagged electron: it has barely moved. Drift is slow, the signal is fast.

More push, more flow; more resistance, less flow

1. A resistor (zig-zag) makes electrons bump into atoms. Its size is R, in ohms (Ω).
2. The ammeter reads current I = V / R. Drag V up: dots speed up, the needle climbs.
3. Drag R up: the same push gets less current through.
4. The graph: current against voltage is a straight line, slope = 1/R. The dot is your setting.
5. What sets R? A wire's length L, its cross-section A and its material ρ: R = ρ·L / A. Switch materials.

Every resistor turns electrical energy into heat

1. Power = energy per second, in watts (W). For anything electrical: P = V × I.
2. In a resistor that energy becomes heat. Push I up: the block glows, the thermometer climbs. Since V = IR, P = I²R.
3. The ladder compares real things on a log scale (each step ×10): an LED 0.06 W … a big AI chip ~700 W.
4. Chips run at low voltage (~1 V), so 700 W means ~700 A. Even a tiny wire resistance then wastes I²R as heat.
5. That heat has nowhere to go but out through the top: heatsink, fan, liquid. Power is a hard wall for chips.

Two resistors in a row split the voltage

1. Series: R1 on top, R2 below, one path. The same current flows through both.
2. The supply's 5 V is shared: the bar shows how much each resistor "uses". Bigger R, bigger share.
3. The node between them sits at V·R2/(R1+R2). Drag R1 small and R2 big: node goes high.
4. That is how a gate makes a 1 or 0: a switch that is ON (tiny R) against one that is OFF (huge R) pins the node near VDD or near 0.
5. Parallel: two paths side by side. Currents add, total resistance drops below the smaller one.

A capacitor fills up, and it takes time

1. Two plates with an insulator between them. Charge cannot cross the gap.
2. Close the switch: electrons flow onto one plate and off the other. A voltage grows between them.
3. The graph draws the plate voltage live. Fast at first, then slower: less push is left as it fills.
4. The dashed line marks τ = R·C: at that moment it is 63% full. Stored charge Q = C·V.
5. Change R or C and close again: bigger either one → longer τ → slower filling.

Inside a chip every wire is a tiny capacitor, so switching takes time and power

1. A transistor that is ON acts like a resistor (R_on) connecting the wire to VDD.
2. The wire and every gate input it drives are small capacitors to ground. They all add up to C.
3. So a 0→1 is an RC charging curve. Delay ≈ 0.69·R·C (the red mark). Raise fan-out: slower.
4. Raise the clock f: past a point the wire never reaches a clean 1 (red). This sets a chip's top speed.
5. Every cycle dumps C·V² of energy as heat: P ≈ α·C·V²·f. 100 million nodes at α = 0.1 turns tens of µW each into hundreds of watts.

Why computers use only 0 and 1: noise gets ignored

1. Eight bits are sent as 3.3 V (1) or 0 V (0). The wire adds random noise.
2. The receiver has two lines: above VIH = 2.0 V means 1, below VIL = 0.8 V means 0. Between is forbidden (red).
3. It reads each bit in the middle of its slot. With a little noise, every bit comes out exactly right.
4. The bottom row: an analog receiver reading the same wire gets a wrong value every time, by the full noise amount.
5. Drag noise up. Digital stays perfect until noise spikes reach the red forbidden zone, then bits start to fail. Press new noise to retry.

Charge never piles up at a junction, and voltage around a loop always sums to zero

1. A node is any junction. Currents A and B flow in from the left.
2. All of it must leave: out = A + B. Charge never piles up at a node. Drag A or B and watch the output grow.
3. A loop: the battery raises 5 V, the resistors drop it back. The staircase on the right always returns to 0.
4. Change A or B: the drops re-share, but they always add up to 5 V.
5. A short circuit: a wire straight across the battery. R ≈ 0, so I = V/R is huge, and I²R melts it.

Where LPULite hits these limits: its clock is 8× slower than the board's

1. The FPGA chip gets power on separate pins: 1.1 V for the core logic, 3.3 V / 2.5 V for talking to the outside (I/O).
2. The board's crystal gives CLOCK_50: a tick every 20 ns. Each tick, results must finish racing through the logic.
3. The longest path (the critical path) is a chain of gates and wires, each an RC delay. Quartus's Fmax of 9.84 MHz means it takes ~101.6 ns.
4. Try ÷4: 80 ns per tick. The path is still running when the next tick arrives: timing failure (red).
5. ÷8 = 6.25 MHz, 160 ns. The path finishes with 58.4 ns slack (green). This is what LPULite ships.

Why does silicon conduct only a little?

1. A silicon atom has 4 outer electrons. It shares one with each of 4 neighbours, so every bond holds 2 electrons.
2. Those bond electrons sit on the valence band, the low rung of an energy ladder. Moving freely needs the high rung: the conduction band.
3. The gap between the rungs is the bandgap: 0 for copper, 1.12 eV for silicon, ~9 eV for glass.
4. Heat shakes a few electrons loose. Each free electron leaves a hole in its bond: an electron–hole pair. Drag the temperature.

A hole is a missing electron that seems to move

1. A row of bonds, all full except one: the empty spot is the hole (open red circle).
2. A battery pulls electrons toward + (right). The electron just left of the gap hops in.
3. Read the timeline rows top to bottom: each electron moved one step right, but the hole walked left.
4. So a hole acts like a positive charge moving the opposite way. In silicon it is about 3× slower than an electron (mobility ≈450 vs ≈1400).

Add one foreign atom per ~5 million and silicon conducts

1. Pure silicon: every electron is locked in a bond. Almost no carriers.
2. Swap in phosphorus (5 electrons). The 5th has no bond, so it wanders free: n-type.
3. The phosphorus that lost it becomes a fixed + ion. It cannot move — only the electron can.
4. Swap in boron (3 electrons). One bond is short: a hole that wanders, and a fixed − ion.
5. Right chart (log scale): the added carrier is the majority (10¹⁶); the other kind drops to a tiny minority (10⁴). Toggle freely now.

Press p onto n and a wall builds itself

1. Two separate pieces. p: holes + fixed − ions. n: electrons + fixed + ions. Each piece is neutral.
2. Touch them: carriers diffuse across the boundary, meet, and recombine (flash).
3. What is left at the boundary: fixed ions only, no free carriers — the depletion region.
4. The + ions and − ions make an electric field that pushes carriers back. It balances at a built-in voltage ≈ 0.7 V.
5. Across the junction: charge (−,+ blocks) → field (a triangle) → voltage (a 0.7 V step).

A diode is a one-way valve for current

Three jobs a diode does every day

A MOSFET is a sandwich: metal, oxide, silicon

1. Start with a block of p-type silicon: the body (substrate), full of holes.
2. Dope two islands heavily n-type: n+ source and n+ drain.
3. Grow a very thin insulator on top between them: the gate oxide (SiO₂ or high-k).
4. Put a conductor on the oxide: the gate. It is insulated from everything below.
5. Wire up the 4 terminals S G D B, and name the sizes: L (length, source→drain) and W (width, into the page).

How a gate voltage creates a wire in silicon

1. Gate at 0 V: holes everywhere, two n+ islands separated by p-silicon. No path.
2. Gate at 0.35 V: holes are pushed away. The exposed fixed − ions form a depletion layer. Still no current.
3. Gate past V_th: electrons are pulled into a thin inversion channel. Electrons flow source → drain.
4. Right: I_d vs V_gs. Almost flat until V_th, then rising like a square. Drag the slider yourself.

Small V_ds: a resistor. Big V_ds: the channel pinches off

1. One curve per gate voltage: drain current vs drain voltage. The thick one is your V_gs; the dot is where you are.
2. Left of the dashed line: linear region. Current ∝ V_ds, so it is a resistor (value shown).
3. Right of it: saturation. The drain end of the channel pinches off and current goes flat.
4. The dashed boundary is V_ds = V_gs − V_th. Drag both sliders and watch the channel taper in the cross-section.

PMOS is NMOS flipped: on when the gate is low

One PMOS + one NMOS = a NOT gate that sips power

1. Input 0: PMOS on, NMOS off. Output is pulled up to 1.8 V. No path to ground → no current.
2. Input 1: NMOS on, PMOS off. Output pulled to 0 V. Again no through-path.
3. Input halfway: both partly on → a brief current spike from VDD to ground.
4. The transfer curve: output snaps from 1 to 0 around the switching point (0.9 V here, where V_out = V_in).
5. Real power is mostly charging the load: P = α·C·V²·f. Drag the slider through the middle and watch the spike.

From 10 µm to "3 nm": and the name is now marketing

A chip is printed in layers, with light

1. Start with a polished p-type silicon wafer. Every layer below is printed by the resist → light → develop → etch loop (right).
2. Implant an n-well where PMOS will live; etch and fill oxide isolation trenches between transistors.
3. Grow the thin gate oxide and pattern the gates (poly/metal).
4. Implant n+ (NMOS) and p+ (PMOS) source/drain, self-aligned to the gates.
5. Cover with insulator and drill contacts; add local interconnect.
6. Stack metal 1 … metal 5 with vias between them. SKY130 stops at metal 5; big modern chips use 10+.

A logic gate as it is actually drawn on silicon

1. Two power rails: VDD on top, GND on the bottom. Every cell in the row has them at the same height.
2. Two strips of doped silicon: p+ on top (inside the n-well) for PMOS, n+ below for NMOS.
3. Two vertical gate stripes, A and B. Each crossing of a gate over a strip is one transistor: 4 in total.
4. Contacts + metal: PMOS in parallel (VDD–Y–VDD), NMOS in series (GND–·–Y). Output pin Y.
5. Toggle A and B: lit crossings conduct. Y is 0 only when both are 1.

Every LPULite unit is, underneath, CMOS transistors

Eight wires make a number. Hex makes it readable.

1. Each switch is one bit. Its place value doubles going left: 1, 2, 4 … 128. Click the boxes.
2. Add the place values of the 1s. That sum is the decimal number.
3. Cut the 8 bits into two groups of 4. Each group (0–15) is one hex digit: 0–9 then A–F.
4. Long words are unreadable in binary, so we write them in hex. A 72-bit LPULite row = 18 hex digits; a 96-bit instruction = 24.

Six gates, each a tiny rule: when is the output 1?

Two different circuits, the same answer for every input

1. Left: AND then NOT. Toggle A and B and watch the output.
2. Right: NOT each input, then OR. A completely different wiring.
3. Check all 4 input patterns: the two outputs agree every time. That is what "=" means in logic.
4. Simplification: A·B + A·¬B always equals A, so 4 gates can be replaced by one wire.
5. Switch to NOT(A OR B): it equals NOT A AND NOT B. Swap AND↔OR and push the NOT inside.

Write any truth table, and the circuit draws itself

1. Click the F column to choose which input rows should output 1.
2. Every input comes as two wires: the true one and the inverted (¬) one.
3. Each row with F=1 gets an AND gate tapping the wires that match that row (dots = connections).
4. One OR gate joins them. Toggle A, B, C: F lights exactly on your marked rows.

A MUX is a switch controlled by a number

1. The idea: a rotary switch. The select number turns the arm to one input. Click D0/D1 and the select button.
2. Inside: an AND gate per input. D0's AND opens only when select=0, D1's only when select=1. An OR joins them.
3. 4:1: two select bits make 4 patterns, so each AND checks both bits.
4. A bus = 8 (or 72) copies sharing the same select wires, steering a whole number at once.

A decoder turns a number into exactly one lit wire

1. The address is a small number on 3 wires. Click the bits.
2. An inverter gives each bit a ¬ copy, so every pattern can be matched.
3. One AND per output, tapping the pattern it recognises. Exactly one output is 1: one-hot.
4. That one hot line switches on one memory row (its word line).
5. Encoder = the reverse. Click the request boxes: the priority encoder outputs the highest number that is on.

Comparing numbers is just gates, and ReLU is a comparator plus a MUX

1. Equal? XNOR each bit pair ("same?"), then AND all four. Drag A and B.
2. Less than? Subtract. If A − B is negative, its sign bit is 1.
3. ReLU: the sign bit of x is the select of a MUX. Negative → pick 0, else pick x. Drag x. This is the exact line in LPULite's VXM.

From one column of addition to 8 bits, with the carry racing left

1. Half adder: 1+1 = 10 in binary. Sum bit = XOR, carry bit = AND.
2. Full adder: add a carry-in with a second half adder; an OR merges the two carries.
3. 8-bit ripple: press launch. Red sums are not settled yet; the carry needs 2 gate delays per stage.
4. Subtraction: flip every bit of B, set carry-in = 1, and the same adder computes A − B.

Sliding bits sideways multiplies or divides by 2

1. Shift left: every bit moves one place up; a 0 enters on the right. Value × 2.
2. Arithmetic shift right: the sign bit is copied in. −6 >>> 1 = −3, so value ÷ 2 even when negative.
3. Logical shift right puts a 0 in instead: −6 becomes 125. Wrong for signed numbers.
4. Barrel shifter: drag "amount". Layer 1 shifts by 1, layer 2 by 2, layer 3 by 4; each layer's MUXes obey one bit of the amount.

Every gate takes time, and the slowest path sets the chip's speed

1. Each gate adds 1 unit of delay. The circuit computes F = A·B + ¬A·C.
2. The critical path (blue) runs A → NOT → AND → OR: 3 gates. Every other path is 2.
3. The replay shows A falling 1→0 (B=C=1). Watch the time stamps: the short path turns off before the long path turns on, so F drops to 0 for one unit: a glitch. (A rising never glitches here: if you just made A rise, press flip A once more.)
4. Turn on the extra term B·C: it holds F at 1 during the race. Flip A again: no glitch.

Compute every answer at once, then let a MUX pick one

1. Two 8-bit inputs A and B arrive on buses. Drag them.
2. Six blocks compute all six answers at once: adder, subtractor, AND, OR, XOR, shift.
3. The op code is the select of a 6:1 MUX. Click an op: only the arm moves, nothing is recomputed.
4. Flags: Z = result is zero, N = sign bit, C = carry out.
5. This is execute in fetch → decode → execute → write back.

Where LPULite uses MUXes, slices, comparators, shifts and adders

1. Bus = MUX. The select number picks which unit's 72-bit row drives the westbound bus. Drag select.
2. ICU fields: instruction bits [2:0] are wired straight to the bus select. No decoding, just a slice of wires.
3. VXM: add bias → ReLU (sign bit picks 0) → ÷2 (>>>1). Each stage has a bypass MUX set by a ctrl bit.
4. Quant: shift right until the biggest value fits in 8 bits, then round-shift every lane by the same amount.
5. MAC: multiply, shift to line up scales, then add into the accumulator.

Some circuits forget instantly. Some remember.

1. No memory: a lamp wired to a button is ON only while held. Press it — after release it is always off.
2. Memory: a toggle cell. Same press, but the lamp's state depends on how many presses came before. That is “sequential”.
3. Where does memory come from? Feedback. Two NOT gates in a ring: B = NOT A, and A = NOT B. The loop agrees with itself.
4. The value circulates forever while powered. Kick the loop — force A from outside — and it flips and holds the new bit.

Two NOR gates holding hands make an SR latch

1. Start with two NOR gates. A NOR outputs 1 only when both its inputs are 0.
2. Cross-couple them: Q feeds the lower gate, Q̄ feeds the upper gate. That feedback loop is the memory.
3. Press S: Q becomes 1. Release it: Q stays 1 (HOLD). Press R: Q becomes 0 and stays.
4. The timing trace records every change: Q only moves when S or R is pressed.
5. Now press S and R together: both outputs go 0 — the forbidden row, drawn red. Release both: a random race.

A D latch: a window that is open or shut

1. D goes straight in, and through a NOT. Two AND gates let them through only when EN = 1: S = D·EN, R = D̄·EN.
2. S and R drive the SR latch from the page before. S and R can never both be 1 — no forbidden case.
3. EN = 1: transparent, Q follows D live. EN = 0: hold, D can wiggle and Q ignores it. Try both switches.
4. The recorder: Q copies D only inside the yellow columns (EN high). Press Run time and flip D and EN.

Two latches back to back change only on the clock edge

1. Put two D latches in a row: a master and a slave.
2. The clock drives them opposite ways: master EN = NOT CLK, slave EN = CLK. Never both open.
3. Press Clock. CLK = 0: master open (listens to D), slave closed (Q holds). CLK = 1: master freezes, slave shows it.
4. Waveforms: the plain latch follows D all the time CLK is high…
5. …but the flip-flop Q changes only at the red ↑ rising edges. One snapshot of D per tick.

A flip-flop needs D still around the edge — or it can't decide

1. One rising clock edge at t = 0, the D input changing from 0 to 1, and the output Q.
2. Setup time: D must already be steady for a short window before the edge.
3. Hold time: D must stay steady for a short window after the edge too.
4. Clock→Q: even when all is well, Q appears a little after the edge.
5. Drag D's change into the window: Q goes metastable (red wobble) and falls to 0 or 1 unpredictably.

Reset now or reset at the tick — and how a flop holds

1. A clock with 8 ticks and a reset pulse. Drag where it starts and how long it lasts.
2. Asynchronous reset: Q drops the instant rst rises — no clock needed.
3. Synchronous reset: Q drops only at the next rising edge while rst is high. Make the pulse short → it is missed.
4. Enable is a MUX: EN=1 loads new D, EN=0 feeds Q back into D so it holds. Flip EN.

A register is just a row of flip-flops sharing one clock

1. One D flip-flop stores one bit.
2. Eight side by side, fed by an 8-wire D bus, driving an 8-wire Q bus. Drag the value — Q waits.
3. They all share one clock wire, so all 8 bits update on the same edge. Press Clock tick.
4. A shared enable: set EN = 0 and ticks do nothing — the register holds.

Chain the flops and bits march one step per tick

1. Eight flip-flops in a chain: each Q feeds the next D.
2. One shared clock. Press Clock tick: every bit moves one stage right, the last one falls out.
3. Set serial in and keep ticking: your bits come out the far end, in order.
4. Uses: serial links (one wire, a bit per tick) and delay lines (out = in, 8 ticks later).

A register plus a +1 adder counts — that is a program counter

1. A register holds the count. The ring shows all 2^N values it can hold.
2. Its output goes through a +1 adder and back into its own input: each tick loads old+1. Keep ticking — it wraps to 0.
3. A MUX can pick a load value instead: turn on jump, tick, and the count leaps. That is a CPU's jump.
4. The top bit toggles every 2^N−1 ticks: a clock divider. Pick 3 bits — that is how the board makes 50 ÷ 8 = 6.25 MHz.

Data must cross the logic before the next tick — that sets Fmax

1. Flop A → logic → flop B, both on the same clock. Data launched at one tick must be caught at the next.
2. Lay the path on a timeline: clock→Q, then the logic delay, then B's setup.
3. The next tick comes at the period. Left over = slack (green). Drag logic past it: violation (red).
4. Fmax = 1 / path. Press LPULite numbers: 160 ns period (6.25 MHz), ≈101.6 ns path (9.84 MHz) → 58.4 ns slack.

Cut a long path with registers: faster clock, but later answers

1. 30 ns of logic between two registers. The clock can tick at most once per 31 ns.
2. Choose 2 or 3 stages: extra registers (black bars) cut the path.
3. Press Clock tick: every token moves one stage per tick, a new one enters each tick.
4. Trade-off: results per second go up (green), but each answer waits N ticks (red). Balance the cuts.

A state machine = a register that remembers “where am I”

1. Next-state logic (gates) decides where to go; the state register (flip-flops) stores it at each clock tick.
2. The current state is fed back into the next-state logic — the same feedback idea as the latch.
3. Output logic turns the state into outputs. Toggle Moore / Mealy: Mealy also wires the inputs in.
4. A traffic light: 4 bubbles (states), arrows labelled with conditions. Toggle car waiting, press Clock tick.
5. The whole “where am I” is just 2 bits in a register. In Mealy mode the WAIT lamp reacts to the car without a tick.

“Start” → busy → “done”: the handshake every hardware block speaks

1. Three states. start = 1 takes IDLE → BUSY; BUSY counts 3 ticks; DONE lasts one tick, then back to IDLE.
2. Outputs come straight from the state: busy = in BUSY, done = in DONE.
3. The waveform: turn start on, tick, turn it off — watch the state row walk I → B → B → B → D → I.
4. busy is high for the work, done pulses for exactly one tick. That pulse is the “finished” message.

Now read LPULite's real state machines, one tick at a time

1. Pick a unit. The bubbles are its states, the arrows carry the real signal names from the file. Yellow = current state.
2. Right: the real SystemVerilog lines with their line numbers. Press Clock tick — the lines that ran light up.
3. Flip the input switches (start_i, out_ready, wr_en…) and tick: you are the testbench.

Where LPULite remembers: 10,031 flip-flops

1. The fitter's count: 10,031 flip-flops in LPULite's FPGA build.
2. That is the chip's short-term memory. Clock 6.25 MHz; slowest path 9.84 MHz; 58.4 ns spare.
3. Filter by kind — state machines, counters, FIFOs, timing — and click a card to jump to the unit.

Memory is a wall of numbered boxes

1. Each box has a number (its address) and holds an 8-bit value. Hover any box.
2. Flip the address switches: 4 wires pick 1 of 16 boxes.
3. Read: the chosen box's bits are copied onto the output. The box keeps them.
4. Write: drag a new value, press write. Write enable = 1 for a moment and the old value is gone.

Fast memory is tiny, big memory is slow

1. Register: flip-flops inside the logic. Fastest, holds only bytes.
2. SRAM: on the processor chip. ~1 ns, but very expensive per bit.
3. DRAM: separate chips. ~50 ns: already ~50× slower.
4. Flash SSD: microseconds. Holds terabytes.
5. Disk: milliseconds — ten million times slower than SRAM.
6. Switch between size, access time and cost: every row wins one and loses another.

An SRAM bit is two inverters holding each other

1. Two inverters in a loop: Q feeds inverter 2, QB feeds inverter 1. The green transistors are ON. It holds the bit by itself.
2. Word line + two access transistors (M5, M6): the doors between the cell and the outside.
3. Bit lines BL and BLB run down every column to a sense amplifier.
4. With read selected, press next phase 3 times — precharge, open word line (watch current drain one bit line), sense.
5. Press write, set the write value, press next phase: drivers force the bit lines, the word line opens, the cell flips.

A DRAM bit is a leaking bucket of charge

1. Press hold. One transistor (door) and one capacitor (bucket). Full bucket = 1.
2. Press read (share): the door opens and the charge spills into the big bit line. It moves only +45 mV, and the cell is now destroyed.
3. Press rewrite: the sense amplifier pushes a full 1 back in. Every read ends with a write.
4. The bucket leaks. Drag the leak slider to fast, then turn refresh OFF: the bit is lost. Refresh every 64 ms saves it.

A memory chip is cells in rows and columns

1. 32 cells: 4 rows (words) × 8 columns (bits). Hover a cell.
2. The row decoder: one AND gate per row. Only the one matching the address outputs 1.
3. That row's word line lights; all 8 cells drive their bit lines at once. Click another address.
4. Sense amplifiers clean the bits and put the whole word on the data bus.
5. The column mux picks one bit from the word. Drag it.

Synchronous memory answers one tick late

1. The clock: every rising edge is one tick. Press play.
2. The address and read enable must be steady around the edge: setup before, hold after.
3. Synchronous RAM: data appears only after the next edge — 1 tick late. Compare ideal async.
4. So LPULite's compiler writes the same read twice; the consumer captures on the second tick.
5. The exact Verilog below: stream_out <= sram_array[addr] inside posedge clk is the register that causes the delay (simulation model; the FPGA altsyncram adds an output register).

A memory can be a function

1. The exp table: 178 rows burned into LPULite's softmax. Drag a.
2. The address is the input, the stored number is the output. No maths happens at run time.
3. Plotted, the rows are the curve 256·e^(−a/256): from 256 down to 128.
4. An FPGA LUT is the same idea: 4 inputs address 16 bits. Flip inputs, switch the function.

LPULite fills 79% of the FPGA's memory tiles

1. Each square is one M10K hard memory tile. There are 397. Press fill the tiles.
2. MEM0 and MEM1 take 144 tiles each, IMEM 10, row FIFOs 9 + softmax score buffer 7 = 16.
3. Quartus reports 79% of tiles but only 61% of bits.
4. Why: each memory's bits are spread over more tiles than bits alone would need.
5. One row is 72 bits: 8 int8 lanes + an 8-bit scale. × 16,384 rows = 144 KiB.

The CPU talks to the FPGA by writing to addresses

1. The ARM CPU runs Linux and sees a window of addresses starting at 0xFF200000.
2. The window is split in four: IMEM, MEM0, MEM1, control. Pick one.
3. One row = 3 × 32-bit writes at base + row × 12. Press send write; word 2 commits.
4. Pick control: one write of 1 to 0xC000 starts the chip running.

A FIFO is a queue made of two chasing pointers

1. 4 slots in a ring. Press push a few times: the green wr_ptr moves on.
2. Press pop: the red rd_ptr takes the oldest item first.
3. Push until FULL lights: the next push is refused. Pop to empty: EMPTY. This is the real LPULite code.
4. Keep pushing and popping: the pointers wrap from 3 back to 0.

For AI, the pipe from memory is the bottleneck

1. Memory holds all the weights; compute needs every one of them for each new token.
2. Width: how many wires in parallel. Drag it.
3. Speed: bits per second on each wire. Watch the bytes flow.
4. tokens/s ≤ bandwidth ÷ model size. Make the model bigger: the ceiling falls.

Every memory inside LPULite

Verilog is not a program that runs. It is a drawing of wires.

1. Software: the CPU runs ONE line per time slice. Watch the red ▶ and the blocks fill one by one.
2. Verilog lines are not steps. Each line names a part. Hover one.
3. The four lines become four gates. In every slice, all four are working — no waiting.
4. Shuffle the lines: it is still exactly the same circuit. Order doesn't matter.

A module is a box with named pins

1. module adder … endmodule = the outline of one box named adder.
2. input logic [7:0] a: eight wires come in. Drag a and b — each wire is 0 or 1.
3. output logic [8:0] y: nine wires go out. The top one is the carry.
4. Open the box: assign y = a + b is an adder circuit, always computing.

Slicing and gluing bits is just choosing wires

1. x[7] is one wire: the sign bit of a signed number. Flip x7 above.
2. x[3:0] is a slice: the bottom 4 wires.
3. { , } glues bundles: here the two halves swap places.
4. {{8{x[7]}}, x} copies the sign bit 8 times: a 16-bit number with the same value.

assign and always_comb build logic with no memory

1. assign y = a & b = one AND gate. Flip a and b: y follows instantly.
2. always_comb + if/else = a MUX (a wire selector). Still no clock.
3. Flip sel: the red path moves from b to a. Both inputs are always connected.
4. “Comb” = no memory. Change an input and the output changes a fraction of a nanosecond later (the gate delay).

always_ff builds memory that updates on the clock edge

1. always_ff @(posedge clk) becomes a D flip-flop: one bit of memory.
2. Set d = 1. Look at the waveform: q does not move.
3. Clock tick: at the rising edge (red line) q copies d.
4. q <= d = “q becomes d at the edge”. Try Auto clock and flip d between ticks.
5. Many flip-flops on one clock = a register. LPULite's FPGA build has 10,031.

<= swaps two registers. = silently breaks the swap.

1. Two registers: a = 3, b = 7.
2. With <=: read all right sides first, update all at the edge. Tick!
3. They swap. The circuit is two flip-flops with crossed wires.
4. Switch to =: line 1 changes a before line 2 reads it.
5. Now b just feeds itself: both hold 7 and the swap is lost (red row).

An enum, a register and a case make a state machine

1. typedef enum logic [1:0]: names for 2-bit codes. IDLE = 00, LOOKUP = 01, DONE_ST = 10.
2. always_ff: a 2-flip-flop state register in the RTL. always_comb: the next-state logic, fed back in a loop.
3. Each case branch is an arrow. Hover lines 366-367: the IDLE → LOOKUP arrow.
4. Set start = 1, then press Clock tick: IDLE → LOOKUP.
5. Tick again: DONE_ST with done = 1 for one clock, then back to IDLE.

Modules go inside modules — LPULite's top box, and loops that stamp out copies

1. One instance line has 4 parts: module, #(parameters), instance name, (pin connections).
2. The top box lpu holds icu, two copies of mem, sxm, three row_fifos, plus the bus blocks (westbound_bus, eastbound_bus, their decoders, mxm_eastbound_adapter — lpu.sv:401-481).
3. mxm holds 64 MACs; vxm holds softmax, rmsnorm, quant, residual_add, vxm_rope.
4. A generate for loop stamps out one copy per lane. Drag the loop count.

A packed struct is a bus with named bit ranges

1. One westbound row = 72 wires. typedef logic [71:0] westbound_row_t just names that shape.
2. struct packed cuts it: row_scale = bits 71…64, packed_row = bits 63…0 (8 lanes).
3. Meaning: value = lane × 2^row_scale. Drag row_scale: the lanes' bits don't change, the meaning does.

A testbench wiggles the inputs and checks the answer

1. The testbench makes the clock and instantiates the real quant.sv as dut.
2. Press Step time: the red cursor moves 5 ns. Hold reset for 2 edges, then release.
3. Put 256 (= 1.0) on lane 0 with in_valid; 2 edges later out_valid rises with 32. The check passes.

Synthesis turns text into gates, then into a real FPGA

1. Your Verilog: a 3-bit count register and empty = (count == 0). Flip the count bits.
2. Logic synthesis: 3 flip-flops and one NOR gate.
3. Mapping: the NOR becomes a lookup table — 8 stored bits. The yellow row is the one being read.
4. Place & route: each cell gets a spot on the grid; wires are routed between them.
5. Bitstream: one file that sets every LUT bit and routing switch on the Cyclone V.
6. All of LPULite went through this: 100% of logic and 100% of DSP blocks used.

Read a real LPULite file end to end: row_fifo.sv

1. Ports (lines 3-15): parameters DATA_W and DEPTH, then the pins.
2. Storage (19-22): 4 rows, two pointers, a count.
3. Comb (24-26): data_out = mem[rd_ptr] is a MUX; full/empty are comparators.
4. Flip-flops (28-40): press Write twice and Read once — watch the pointers.
5. Case (43-47): count goes +1, −1 or stays. Fill it: full = 1 blocks writes.

Where LPULite uses all of this

wire, reg, logic are the same bits — until two things drive one

1. One driver: assign y = a; — a single, legal source. Flip a.
2. Switch to two drivers (bug): assign y = a; assign y = b; — the same wire, twice.
3. When a ≠ b the wire has two different demands at once: real hardware shorts, simulation prints X.
4. LPULite's fix pattern: each producer drives its own slot in an array; a MUX (not two wires tied together) picks one. Hover the bus diagram.

4 bits + 4 bits into a 4-bit box: the answer's top bit vanishes

1. Drag a and b (0–15 each). The adder always computes the true 5-bit sum first.
2. y is [3:0] (bug): the top bit is sliced off before it reaches y. Push a+b past 15 and watch y wrap.
3. Switch to [4:0] (fixed): one more wire and the same sum is exact, every time.
4. Read the bottom panel: this exact y=a+b form is invisible to Verilator's lint; the real LPULite address-truncation bug (a wide slice into a narrow port) is the shape a lint tool actually catches.

Forget signed and −5 becomes 251

1. Drag the input lane negative. Its 8 raw bits are shown — they never change.
2. signed [7:0] (mac.sv): those bits read as −5. Product = −5 × 20 = −100. Correct.
3. Switch to unsigned (bug): the exact same bits now read as 251, and (in this mode) the multiply also drops the $signed() cast, reading the raw fields directly. Product = 251 × 20 = 5,020.
4. Off by 5,120 — from dropping signed and skipping the $signed() cast. Either one alone would not have been enough to break it: the MAC's real code carries both as independent safeguards.

Forget the else in always_comb and you built a latch

1. Drag sel through 0,1,2,3. In No default (bug), watch y for sel = 3.
2. sel = 3 matches no branch. always_comb can't leave y undriven, so the tool infers a latch (the looped SR gate lights up).
3. y now holds its last value instead of computing one — a silent memory element nobody designed.
4. Switch to unique case + default: sel = 3 now hits default, y is always driven, the latch disappears.

Reset can happen any time, or only on the clock — pick one on purpose

1. Set d = 1, tick the clock: q copies d, same as the basic flip-flop.
2. In Async mode, press Assert rst_n now mid-cycle (no tick): q drops to 0 instantly — the waveform shows it between edges.
3. Switch to Sync, assert rst_n again: q does not move until the next Clock tick.
4. Turn en off and tick: q holds even though the clock still ran — en is a separate hold, not a reset.

One generate for loop writes 64 copies of one MAC

1. The loop body is one line: an instance of mac, wired to row r's input and column c's weight.
2. Drag mxm_size down from 8: the grid shrinks — the tool builds exactly N×N real copies, not one shared circuit reused N² times.
3. At 8, that's 64 independent MAC circuits, each with its own accumulator register, all working the same instant — the same "every gate is always on" idea from page 1 of part A6, at chip scale.

An array of registers becomes a real memory only if the read is synchronous

1. Write row: sram_array[addr] <= data_in inside always_ff — an ordinary register write.
2. Read row in Sync (mem.sv): the address goes in, and the data appears one clock later — that one-cycle delay is the signature of block RAM.
3. Switch to Comb read (bug), read again: data appears the same cycle — looks convenient, but it can no longer map onto the chip's dedicated RAM.
4. At 16,384 rows, that difference is thousands of flip-flops the tool has to build instead of one hard macro.

Two real bit layouts: a struct that names its fields, and one that doesn't

1. westbound_fixed_row_t: hover a field name — its exact 8 or 64 bits light up in the 72-bit strip.
2. Reading row.row_scale costs 0 gates: it's just "look at wires 71 down to 64", same as bit slicing.
3. Switch to the 96-bit VLIW word: the same idea, 12 fields, but named only in a comment and 12 separate assign lines.
4. Hover a field here too — same mechanism, no struct required, just more places a mistyped index can go unnoticed.

A queue that doesn't check full quietly overwrites data

1. Press Write four times: rows fill 0→3, full lights up on the 4th.
2. Press Write a 5th time in row_fifo.sv (correct) mode: nothing changes — the guard blocks it, count stays 4.
3. Switch to no full-check (bug) and write again: row 0's data is overwritten — the value you wrote first is gone, silently.
4. Now Read: you get back the corrupted row 0, not the original data. No error anywhere in the waveform.

Same state machine, two ways to type it

1. 2-process: the top block is pure state <= next_state — nothing else. Tick and watch it only ever copy.
2. The bottom always_comb works out next_state from state and start, and never touches a register.
3. Switch to 1-process: one block does both jobs — if (state==IDLE && start) state <= LOOKUP; ….
4. Tick through IDLE→LOOKUP→DONE_ST in both styles: identical waveform, identical hardware — the difference is only how easy the code is to get right as it grows.

A function becomes gates. $display becomes nothing

1. Drag value above 127 or below −127: clip_signed_q8 saturates it to 127 or −127 — real combinational logic, three comparators and a mux.
2. Inside ±127 the function is a pass-through wire, zero extra gates.
3. Look at the greyed-out lines: #5, initial, $display would be rejected (or silently dropped) by a synthesis tool — they only mean something to a simulator.

Write the test that would have caught the bug before the chip did

1. Clock free-runs. Reset holds for 2 edges (grey), then releases.
2. accumulate(2,1,-4,0) then accumulate(3,1,-2,0) — press Run next check to send them.
3. The tb computes expected = 14, scale = −4 by hand (in the comment) and compares against acc_o/acc_scale_o.
4. Run the reverse-order check: same two numbers, opposite arrival order — must still equal 14.
5. Every check is green; a real mismatch would print red and halt with $fatal, not silently continue.

Read a waveform: the cursor is on the wrong edge

1. Press Step cursor repeatedly. In Read too early, the red cursor lands on the edge right after addr changes.
2. At that edge the RAM's internal register hasn't captured the new address yet — data_out is still the old / power-up (0) value.
3. Every logit reads 0 → argmax always picks token 0 = "a" → the printed word is sata, letter by letter, below the trace.
4. Switch to Fixed: the cursor is placed one edge later — exactly where the registered data_out has the real value — and the printed word becomes correct.

Every construct here maps to a real file you're about to write

1. wire/reg/logic + drivers → every module's ports, and westbound_bus.sv's mux.
2. widths, signed math → mac.sv's signed [7:0] lanes — get this wrong and every MAC in the chip is wrong.
3. always_comb, latches, case → quant.sv's mode mux; always_ff, reset → every register in lpu.sv.
4. generate → mxm.sv's 64 MACs; arrays/memory → mem.sv's 16,384-row SRAM.
5. structs, FSMs, FIFOs, testbenches, waveforms → lpu_pkg.sv, lut_softmax_div.sv, row_fifo.sv, and the debug flow that found sata.
6. Ready: go build the first real module →

A computer only knows one thing: is this wire on?

A transistor is a switch that electricity flips

Wire switches together and you get logic

From one kind of gate, build every gate

1. NOT = a NAND with its inputs tied together.
2. AND = NAND, then NOT.
3. OR = NOT both inputs, then NAND.
4. XOR (“are they different?”) = four NANDs.

A few gates in a row can add numbers

Eight bits, two meanings: how chips store negative numbers

Multiplying is just shifting and adding

1. Multiply 13 × 11 in binary: 1101 × 1011.
2. Each 1 in the bottom number keeps a shifted copy of the top number.
3. A 0 contributes nothing.
4. Add the copies: 10001111 = 143. That is the whole trick.

A chip remembers by waiting for the clock tick

Two ways to store a bit: fast and big vs small and slow

1. SRAM: two inverters feeding each other hold the bit forever (while powered).
2. Two access switches connect it to the read/write lines. 6 transistors, very fast.
3. DRAM: one switch and one tiny capacitor. Much denser.
4. But the charge leaks — it must be refreshed every few tens of milliseconds, and it sits off the main chip.

A normal computer: one worker fetching from far-away memory

1. The program counter points at the next instruction.
2. Fetch: pull the instruction across the bus from memory.
3. Decode: work out what it asks for.
4. Execute and write back. Then repeat — every step crosses the memory gap.
5. To hide the waiting, CPUs add caches and guessing. Fast on average, unpredictable in timing.

Add a fraction to an integer, for free

1. Same 8 bits as INT8 — click any of them below. They start reading 107, a plain integer.
2. Now drag fraction bits. A red line — the binary point — slides in from the right. The bits never move; only the reading changes.
3. Name it Qm.f: m bits before the point, f after. Value = raw integer ÷ 2^f.
4. LPULite's RMSNorm reciprocal lives in Q1.15: 1 bit before the point, 15 after, in a 16-bit word.
5. Its softmax divider needs a bigger word for extra range and precision: Q2.30, in 32 bits.

Build a floating-point number by hand

1. Take 6.5. In binary: 110.1.
2. Normalize it like scientific notation — slide the point until one digit sits before it: 1.101 × 2².
3. Store the exponent as true exponent + bias (127): 2+127 = 129 = 10000001.
4. Store the mantissa as the bits after that leading 1 — "101", zero-padded to 23 bits. The leading 1 itself is never stored; it's implied.
5. Below: all 32 bits for 6.5 are lit up. Click any bit to change it and watch the decoded value update live.

Why 0.1 + 0.2 ≠ 0.3 on almost every computer

1. Watch the digits of 0.1 in binary appear one at a time below — computed live by repeated doubling, the same trick you'd use to convert any fraction.
2. Drag bits kept down to 1 or 2: the stored value is way off 0.1.
3. Drag it up toward 23: the error shrinks fast — but the pattern never stops repeating, so it never hits exactly zero.
4. Two numbers, each with their own leftover error, get added. The sum's error doesn't cancel — it's essentially a coin flip whether it lands on the rounded 0.3 or one tick away.

Every number format is a trade: range against precision

Push a number past its limit: wrap or stick?

1. The dial and bar below track an 8-bit signed register as its true value is dragged from −260 to +260.
2. Inside ±127, both modes agree.
3. Push past +127 in wraparound mode: the stored value jumps to −128 and keeps counting up from there — a huge, silent error.
4. Switch to saturate: the stored value sticks at +127 (or −127) no matter how far you drag. Wrong magnitude, right sign, no silent flip.

Inside a multiplier: a grid of AND gates, then adders

1. A = 1101 (13) is fixed along the top. B's four bits are the toggles above the figure.
2. Every cell in the grid is one AND gate: row i, column j = A[j] AND B[i]. 4×4 = 16 AND gates, computed all at once — no waiting.
3. A row where B[i]=0 is all zero — that AND gate throws the whole row away for free.
4. The surviving rows, each shifted one place further left, are added with plain adders (the ripple adder you already met) to get the final product.

Booth's trick: turn a run of 1-bits into two additions

1. B = 14 = 1110. Naive shift-and-add: three 1-bits → three rows to add.
2. Drag B. Below, each bit pair is read against its right-hand neighbour and coloured: green = start of a run (add A), red = end of a run (subtract A), grey = nothing.
3. A run of 1s of ANY length becomes exactly one add + one subtract. Long runs (like B=14=1110, or B=7=0111) are where Booth pays off most.
4. Fewer rows to add means a faster, smaller adder tree downstream (next two pages) — this is a pure win, at the cost of slightly trickier control logic.

Why multiply costs so much more than add

1. At n=8: the grid below is 8 rows × 8 columns = 64 partial-product bits to add.
2. Drag n up: the grid grows as n², not n. By n=16 that's 256 bits.
3. A ripple-style sum (one adder row at a time) needs n sequential adder stages — slow for a wide multiplier.
4. A Wallace/Dadda tree compresses 3 rows → 2 rows at every layer, in parallel: the layer count grows only as log₂(n) — the bars on the right compare the two.

The chip's 87 hardened multipliers mostly sit outside the multiply array

1. The MXM tab: 64 MAC cells, each multiplying two 9-bit numbers — the literal heart of every matrix multiply on the chip.
2. Its DSP count: zero. All 17,068 ALMs of logic build the multipliers from LUTs instead — the Cyclone V simply doesn't have 64 DSPs to spare once the rest of the chip needs them too.
3. Switch to VXM: RMSNorm's reciprocal-square-root and softmax's reciprocal-divide (RMSNorm, softmax) use 86 of the 87 DSP blocks between them.
4. So on this chip, "the multiply-heavy unit" and "the unit that uses the hardened multipliers" are two different blocks — a resource-budgeting choice, not a law of nature.

Summing many products needs more bits than any one of them

1. One 8×8 signed multiply needs up to 16 bits to hold its product without overflow.
2. Drag "terms summed" up: the bar on the right — minimum accumulator bits — climbs by one every time the count doubles, not every time it grows by one.
3. At 64 terms that's 16 + 6 = 22 bits minimum.
4. LPULite's real accumulator is 32 bits — 10 bits of spare headroom above the bare minimum, used to align mismatched block scales rather than risk overflow.

Give a whole row of numbers just one exponent

1. Eight sliders below hold LPULite's own worked example: 0.5, −1.0, 0.25, 0, 0, 0, 0, 0.
2. The largest magnitude, absmax, is highlighted — here 1.0 (from −1.0).
3. Scale = ⌈log₂(absmax / 127)⌉ = ⌈log₂(1/127)⌉ = −6. One number for the whole row.
4. Every value becomes an 8-bit integer: round(v ÷ 2⁻⁶), clamped to ±127 → 32, −64, 16, 0, 0, 0, 0, 0. Check: 32×2⁻⁶ = 0.5 ✓, −64×2⁻⁶ = −1.0 ✓.
5. Drag any slider — the scale and every 8-bit lane below recompute live, all sharing whatever the new absmax demands.

One outlier, and a shared scale punishes everyone

1. Seven quiet values (around 3-5) sit fixed on the left; one outlier on the right starts near them too.
2. Drag the outlier slider up. Watch the shared scale jump, and the seven quiet lanes' stored codes shrink toward zero.
3. The bar chart on the right shows each quiet value's relative error climbing — some approach ±100%, even though those values never moved at all.
4. This is why real quantizers either use small blocks (fewer victims per outlier), or clip outliers separately before choosing a scale.

Every extra bit and every extra step costs picojoules

1. The bars below are every arithmetic operation from Horowitz's ISSCC 2014 table, drawn to scale.
2. Integer operations are consistently the cheapest; floating point's exponent/normalization logic adds real cost at every width.
3. 32-bit float multiply (3.7 pJ) costs about 18.5× an 8-bit integer multiply (0.2 pJ) — the same shape of gap the n² gate-count argument predicted three pages ago.
4. Switch to "operation vs memory": even the most expensive multiply is dwarfed by a single DRAM fetch — roughly 1,000× more energy just to move one number.

Every idea on this page, somewhere on the chip

1. Q-format: RMSNorm's reciprocal table (RMSNorm) is Q1.15; softmax's reciprocal (softmax) is Q2.30.
2. Saturation: the requantizer clamps every lane to ±127; the MAC accumulator inside MAC saturates at ±(2³¹−1).
3. MAC width: 9-bit operands, 18-bit products, 32-bit accumulator, all inside MXM's 64 MAC cells.
4. DSP vs LUT: MXM's 64 multiplies run on LUTs (0 DSP); VXM's RMSNorm and softmax use 86 of the FPGA's 87 hardened DSP blocks.
5. Block scaling: every memory row and bus ("westbound") carries 8 INT8 lanes plus one shared int8 power-of-two scale — the format the quant page first showed, built here bit by bit.

The simplest CPU: one giant slow step per instruction

1. The program counter names instruction 0. Press Next instruction.
2. Fetch crosses the bus to memory — usually the slowest stage.
3. Decode reads the opcode and register numbers.
4. Execute runs the ALU; write-back stores the result and the PC steps forward.
5. Step through all three instructions — notice the cycle bar is the same length every time, even for the fast ADD.

Fix it like a laundromat: start the next load before this one finishes

1. Toggle to serial: each load finishes completely before the next starts.
2. Toggle pipelined: loads overlap — machine 1 is already washing load 2 while load 1 dries.
3. Switch the label to CPU stages: the same grid is now IF·ID·EX·MEM·WB.
4. Drag instructions up — pipelined total cycles grows by 1 per instruction, not by 5.

Overlap breaks when one instruction needs the last one's answer

1. ADD computes R1 in its EX stage, one cycle before it reaches MEM.
2. SUB needs R1 as it enters EX — one cycle too early to read it from the register file.
3. Forwarding off: the pipeline inserts bubbles until the register file has the value.
4. Forwarding on: a wire carries ADD's ALU output straight into SUB's ALU input — zero bubbles.
5. This is exactly the EX→EX forwarding path real pipelines add in hardware.

The other break: the CPU doesn't know which way a branch goes yet

1. The branch enters IF. The pipeline immediately fetches the next instruction behind it, guessing.
2. A second instruction is fetched too, before the branch even reaches EX.
3. The branch resolves in EX: it was actually taken.
4. Both fetched instructions are wrong — they're flushed (turned red, discarded).
5. The real target is fetched instead, 2 cycles late.

Guess better with a tiny memory: the 2-bit saturating counter

1. Four states in a ring: 00 strongly-not-taken → 01 weakly-NT → 10 weakly-taken → 11 strongly-taken.
2. Predict taken when the state's top bit is 1 (states 10 or 11), else not-taken.
3. Each real outcome moves the counter one step toward the correct side — never jumping straight across.
4. Press Next outcome through the loop pattern: the lone N only nudges it to 10, still predicting taken.
5. Try alternating: the counter oscillates between the two weak states and is right only about half the time — no better than a coin flip.

Memory is 200× slower than the chip — so keep a copy nearby

1. An 8-line cache, 4 bytes per line: address bits split into tag | index (3 bits) | offset (2 bits).
2. Press Next access: the address's index picks one of the 8 lines — the only place it's allowed to be.
3. If that line's stored tag matches → hit, 0.5 ns. If not → miss, fetch from memory (~100 ns) and evict.
4. Watch address 4 hit on its very next visit — temporal locality paying off (it misses again later, once its line gets evicted below).
5. Watch two addresses that share an index keep evicting each other — a conflict miss, the cost of "direct-mapped".

Not one cache — a hierarchy, each ring bigger and slower

1. L1: 32 KB, ~4 cycles (~1 ns at 4 GHz) — small enough to check almost instantly.
2. L2: 256 KB, ~12 cycles — bigger, one hop further from the core.
3. L3: 8 MB, shared by all cores, ~42 cycles.
4. DRAM: off-chip. Add ~51 ns beyond L3 — a full-blown memory access is ~100× an L1 hit.

Same maths, same answer — 3 different loop orders, 3 different speeds

1. ijk: for each output cell, walk straight down a column of B — a big stride every step.
2. Press Play: watch the highlighted B-cell jump line to line. Most reads are misses.
3. Switch to ikj: the inner loop now walks a row of B — consecutive addresses, same cache line reused.
4. Switch to tiled: a small block of B is read once and reused for a whole block of outputs before moving on.
5. The distinct cache-lines touched stat drops sharply — same answer, far less memory traffic.

Stop doing it one number at a time — do 8 (or 16) at once

1. Two arrays of numbers, 64 entries each, need pairwise multiply-then-add — a dot product.
2. Scalar: one multiply per instruction — 64 instructions just for the multiplies.
3. Switch to AVX (8 lanes): one instruction multiplies 8 pairs at once — 8 instructions total.
4. Switch to AVX-512 (16 lanes): 4 instructions. Same answer, far fewer instructions issued.

More cores help less than you'd think — the leftover serial part wins

1. Drag fraction parallelizable — the rest is stuck serial, no matter how many cores exist.
2. Drag cores from 1 up to 256 (the slider steps in powers of 2).
3. The bar splits into a shrinking parallel part and a fixed serial part — speedup tracks the whole bar, not just the parallel piece.
4. Push cores high: speedup flattens well short of the core count. That ceiling is 1/(1−P).

Don't let one slow instruction block everyone behind it

1. Instruction 2 is a slow load — it will take 4 cycles to get its data.
2. In-order: instruction 3, though ready, must wait behind it.
3. Toggle to OoO: instruction 3 issues and finishes early, out of program order.
4. All three still commit (become visible) in the original 1-2-3 order via the reorder buffer.

All of that cleverness stops helping the moment the "loop body" is 7 billion numbers

1. Pick a model size — its weights, at 2 bytes each, must all cross the memory bus for one token.
2. Pick a memory: a single DDR5-4800 channel delivers 38.4 GB/s — a JEDEC number, not marketing.
3. tokens/second = bandwidth ÷ bytes-per-token. A 7B model on 1 channel: a few tokens per second, flat out.
4. Switch to int8 (half the bytes) or GPU HBM3 (~87× the bandwidth) and watch the number jump.
5. Either way — this is why AI accelerators chase bandwidth, not clever caching.

Everything that makes a CPU fast also makes it unpredictable

1. Ordinary CPU: press Run it again twice — cache hits/misses and branch guesses differ each time, so cycle counts jitter.
2. That jitter is invisible in throughput benchmarks but deadly for anything needing an exact deadline.
3. Switch to LPULite-style: the schedule was fixed at compile time, not guessed at run time.
4. Run it again — identical cycle count, every time. No cache, no predictor, nothing to be wrong about.
5. That's the trade this whole part has been building to: guess well, on average — or never guess, exactly.

One neuron: multiply, add, then squash

1. Three inputs x₀, x₁, x₂ arrive on wires.
2. Each is multiplied by its own weight.
3. The three products are added together with a bias → z.
4. ReLU(z): if z > 0, output z; otherwise output 0.
5. Drag the sliders — watch z and the output number change live.

A layer is just a matrix times a vector

Learning is sliding downhill on a loss curve

1. The curve is loss(w) for a fixed toy input and target.
2. The dot marks the current w and its loss.
3. The line through it is the slope — how loss changes as w changes.
4. Press one gradient step: w moves opposite the slope, scaled by a learning rate.
5. Repeat — the dot walks down to the minimum.

Backprop: the chain rule, one node at a time

Training carries three extra copies that inference doesn't

1. Inference: weights + one token's activations. Nothing else is kept.
2. Training adds the gradient of every weight — one more weight-sized buffer.
3. Adam adds m and v — two more weight-sized buffers, per-parameter.
4. Activations from the forward pass must be kept, not discarded, until backward finishes with them.
5. Toggle the switch — the bars show what's carried in each mode.

A character becomes a row of numbers

1. Click a letter (or BOS) below the figure.
2. Its token id is just its sorted position — a, b, c… → 0, 1, 2…
3. That id picks out one row of the 27×16 token-embedding table.
4. The model also adds a position row for where the character sits in the word.

Averaging the past is dumb — attention weighs it

1. A plain average weighs every past token the same — it can't tell relevant from irrelevant.
2. Compute Q for the current position, and K, V for every position up to and including it.
3. Score each: Q · Kᵀ — one number per visible position.
4. Causal mask: positions after the current one score −∞ (greyed out).
5. Softmax the visible scores → weights that sum to 1.
6. Output = the weighted sum of the Values — a mix the model actually chose.

Four narrow attentions beat one wide one

1. Split Q, K, V into 4 heads of 4 numbers each.
2. Each head runs attention independently — different relevance per head.
3. Concatenate the 4 head outputs back to 16, then project (attn_wo).
4. Residual add: output = projection + original input.
5. RMSNorm: rescale by 1/√(mean of squares).
6. MLP: widen ×4 → ReLU → narrow back, another residual add.

One transformer block — then stack it

1. Attention sub-layer: normalise → attend → project → + residual.
2. MLP sub-layer: normalise → widen → ReLU → narrow → + residual.
3. That whole box is one block.
4. Drag the slider: stack more blocks, each with its own weights.
5. MicroGPT stops at 1. Llama-3-8B stacks 32.

Logits → softmax → pick → append → repeat

Recomputing every past K and V is wasted work

1. Without a cache: token N recomputes K,V for every earlier position, again.
2. With a cache: each K,V is computed once and stored the moment it's made.
3. Formula: bytes/token = 2 × layers × width × bytes-per-number.
4. MicroGPT: 2 × 1 × 16 × 1 byte ≈ 36 B/token (with LPULite's scale bytes).
5. Llama-3-8B: 2 × 32 × 8 × 128 × 2 bytes = 128 KiB/token.
6. Drag "tokens generated" — the cache grows linearly, one slice per token.

Reading the prompt is parallel; writing new text is one at a time

1. Prefill: every prompt position's matmuls run together — heavy on arithmetic.
2. More arithmetic per weight byte read → compute-bound.
3. Decode: one new token, one more full pass — nothing to share with earlier steps.
4. Every weight must still be read, for very little new arithmetic → memory-bound.
5. Toggle the switch to compare the two shapes of work.

Three numbers price out every model

1. Parameters: MicroGPT 4,192 · Llama-3-8B 8 billion.
2. Multiplies/token ≈ the weight count of the matmuls it runs.
3. Total arithmetic (×++) is commonly approximated as 2 × params/token.
4. Bytes moved/token, minimum: every weight byte must be read once.
5. Toggle the model — the same three formulas, radically different scale.

An AI model is billions of multiply-and-adds

1. Four inputs arrive: x.
2. Each is multiplied by its own learned weight w.
3. The products are added up (accumulated). That's one output.
4. Do this for every output row → a matrix multiply. That is most of an AI model.

A language model writes one token, then runs again

The real bottleneck: moving the weights, not doing the maths

Three bets: a few smart workers, thousands of simple ones, or an assembly line

1. CPU: a few clever cores, caches, guesses. Great at anything, not at bulk maths.
2. GPU: thousands of simple cores doing the same maths in parallel.
3. LPU-style: no guessing — a compiler plans every move; the chip follows the plan, tick by tick.

Groq's idea: fast memory on the chip, and a plan decided in advance

1. A GPU keeps model weights in big, separate memory stacks and ferries them in.
2. Groq's LPU keeps weights in SRAM on the chip — fast, but only ~230 MB per chip.
3. A compiler schedules every operation ahead of time; no caches, no guessing.
4. So big models are spread across hundreds of chips passing data along.

Groq's chip: instructions flow north, data flows east and west

1. The chip is sliced by function, not into identical cores.
2. Instructions flow north from the ICU into every slice.
3. Data streams flow east and west across slices, in parallel lanes.
4. Computation happens where an instruction crosses its data. No caches → same timing every run.

Squeeze every number into 8 bits — with a shared scale

Why 8-bit maths makes a chip so much smaller

Two ways to build a chip: rewire a board or cast your own silicon

1. FPGA: a grid of tiny programmable blocks — lookup tables, flip-flops, memory, multipliers.
2. Programmable wiring connects them. A bitstream sets every switch.
3. ASIC: the circuit is printed permanently into silicon.
4. FPGA: change anytime, slower. ASIC: fastest, but costly and fixed forever.

How an FPGA becomes any circuit: a tiny truth table in memory

Same chip budget, opposite bet: control or arithmetic

1. A CPU core: a little arithmetic, a lot of cache + branch-prediction + scheduling logic around it.
2. A GPU core (Nvidia calls it a CUDA core): almost nothing but an adder/multiplier.
3. One instruction fetch/decode is shared by a whole group of GPU cores — they all run the same instruction.
4. Drag the slider: pack more, smaller cores into the same area — each one gets less control logic, but there are far more of them.

One line of code, run by 65,536 threads at once

Weights live in HBM, a PCIe hop away from the CPU's DDR

1. The GPU die sits on a package next to stacked HBM dies, or on a board next to GDDR chips.
2. A PCIe link (128 GB/s on Gen5 ×16) connects the GPU package to the host.
3. The host's own DDR memory holds the OS, the framework, everything not currently on the GPU.
4. Toggle H100 vs RTX 4090: the data-centre part gets ~3–5× the memory bandwidth of the desktop part.

cuBLAS is fast because it reuses every number it loads

1. Naive: for every output cell, stream a full row of A and column of B from HBM.
2. Tiled: load one small tile of A and one of B into on-chip memory, once.
3. Compute every partial product those two tiles support before loading the next tile.
4. Drag the slider: a bigger tile means each loaded number does more work before it's thrown away.

Decode uses 0.2% of the chip; prefill uses almost all of it

1. H100's ridge point: 1,979 TFLOPS ÷ 3.35 TB/s ≈ 591 FLOP/byte.
2. Decode, batch 1: ~16GB read, ~16GFLOP done → 1 FLOP/byte. Deep in the bandwidth-bound region.
3. Prefill, 2,048-token prompt: weights reused 2,048× → intensity 2,048 FLOP/byte, past the ridge → compute-bound, near peak.
4. Drag decode's batch up past 591: the point crosses the ridge and decode becomes compute-bound too.

More requests per batch: more throughput, slower per user

Every remembered token costs 128 KiB — for real, per sequence

Between two fast kernels, the GPU can just sit there idle

Attention rewritten to never materialise the big matrix

1. Standard attention: compute all of QKᵀ, write the full matrix to HBM.
2. Read it back for softmax, write the result to HBM again.
3. Read again to multiply by V. Three HBM round-trips of a seq×seq matrix.
4. FlashAttention: tile Q/K/V into on-chip SRAM, keep a running softmax, never write the full matrix out.
5. Same exact answer — the saving is entirely in bytes moved, not FLOPs.

One model, many GPUs: split the matrix, or split the layers

One decode step: mostly waiting on weights, barely any maths

The GPU die and its memory are built separately, glued together after

1. The GPU logic die (814 mm² on H100) is fabricated on its own, at TSMC.
2. HBM stacks are fabricated separately, at a memory maker, then pre-stacked with TSVs.
3. Both sit side by side on a silicon interposer — dense short wiring, no active transistors of its own.
4. The interposer assembly mounts on the package substrate that finally meets the board.

For one user waiting on one answer, a GPU is the wrong shape

1. Compute: batch-1 decode uses ~0.2% of peak FLOPs (this part, roofline page).
2. Memory: every token still reads the whole model — the wall doesn't care about batch size.
3. Launch overhead: many small ops per token, each with a CPU-side dispatch cost.
4. Batching fixes throughput but directly hurts the one metric a live user feels: latency.
5. Next: LPULite's machine — no warps, no batching, a plan fixed at compile time.

Who decides what happens next: the chip, or the compiler?

1. A CPU fetches an instruction and only then decides what to do: is this in cache? which way will this branch go?
2. Guess wrong, or miss the cache, and the pipeline stalls — a different number of cycles almost every run.
3. Groq's compiler instead walks the whole program ahead of time and writes down what every unit does, every tick.
4. At runtime the ICU just counts up through that fixed list — there is nothing left to guess.
5. Press Replay: the CPU-style row finishes at a different tick each time; the compiler-scheduled row finishes on the same tick, always.

Inside the chip: instructions flow north, data flows east & west

1. The chip is sliced by function, not copied into identical cores.
2. Every tick, the ICU sends one instruction north into each slice below it.
3. Data streams flow east and west between slices, in parallel lanes.
4. 16 lanes = one superlane; 20 superlanes on-chip → vectors from 16 up to 320 elements.
5. Compute happens where a vertical instruction crosses its horizontal data stream. Click a slice to read its job.

Delete the guessing hardware, and every run takes exactly the same time

1. A CPU/GPU's cache might have your data — or might not. A branch predictor guesses which way an "if" goes.
2. Right guesses are fast; wrong guesses stall the pipeline — a different cycle count nearly every run.
3. The TSP deletes arbiters and caches from its data path entirely — nothing is left that can react differently.
4. Click Run 20 times: TSP-style always lands on the same tick; CPU/GPU-style spreads out.

230 MB of very fast memory — fast enough, but you need hundreds of chips

1. One chip holds about 230 MB of SRAM (first-gen) — plenty fast, but small.
2. A 70-billion-parameter model at 8-bit weighs about 70 GB.
3. 70 GB ÷ 0.23 GB per chip ≈ 305 chips — just to hold the weights, before any compute happens.
4. Drag the controls: bigger models and finer bits need more chips; the newer, bigger-SRAM chip needs fewer.

Chain the chips: each layer on its own chip, the token flows through

1. Packaging: node = 8 chips; rack = 9 nodes × 8 = 72 chips (one node is a spare).
2. A software-defined network carries data chip-to-chip; the compiler schedules it too — same idea as on-chip.
3. Bandwidth per chip: about 50 GB/s at small scale, falling to about 14 GB/s at the largest scale measured.
4. So the interconnect — not the compute — becomes the limit as you add chips.
5. Press Play: watch one token's work move chip to chip through the pipeline.

One user, one stream: milliseconds per token, side by side

1. Every new token needs the model's weights read from memory once more.
2. Groq's measured rate for one user on Llama-2 70B: 241 tokens/second (independent benchmark, Feb 2024).
3. One H200's derived ceiling for a similar-size model, batch 1: about 34 tokens/second — not vendor-measured.
4. Different precision, different chip counts — not a fair fight by itself. Press Play to watch both tick for 200 ms.

Fast for one user is not the same question as cheap per token

1. Reading the weights from memory costs the same whether it answers 1 request or 32 at once.
2. Batch many requests behind that one read, and total tokens/second across all of them climbs.
3. A design tuned for the fastest single-user reply is optimising a different number than total throughput.
4. So "fast per user" and "cheap per token" don't imply each other — check which one a claim is actually about.

2026: Nvidia's Groq 3 LPX — what's published, what isn't

1. Per chip: 500 MB SRAM, 150 TB/s on-chip bandwidth, 96 C2C links at 112 Gbps (2.5 TB/s).
2. One rack: 32 trays × 8 chips = 256 chips, 128 GB total SRAM, 315 PFLOPS FP8.
3. "AFD": Vera Rubin GPUs run attention over the KV cache; LPUs run FFN/MoE, swapping activations per token.
4. Production claim (Aug 2026): 3,400 output tokens/second, Gemma 4 31B, 100K context.
5. Not published anywhere found: die size, clock speed, exact process detail, price.

Google's bet: a matrix-multiply ASIC, chips wired together by light

1. 2017: a 65,536-MAC systolic array — an 8-bit grid where partial sums flow cell to cell.
2. 2017 result: 15–30× faster, 30–80× more TOPS/Watt than a contemporary CPU/GPU.
3. 2023: optical circuit switches dynamically reconfigure the pod network — under 5% of cost, under 3% of power.
4. 2025 (Ironwood): 192 GB HBM and 7.37 TB/s bandwidth per chip — the opposite memory bet from Groq.
5. Scale: up to 9,216 chips per pod, 42.5 Exaflops peak. Toggle the generation to compare.

Cerebras' bet: don't cut the wafer into chips at all

1. A normal wafer is diced into hundreds of separate chips after manufacture.
2. WSE-3 stays whole: 46,225 mm², 4 trillion transistors, 900,000 cores — one chip.
3. 44 GB on-chip SRAM: more than a whole 72-chip Groq rack's combined SRAM, on one piece of silicon.
4. Toggle the cut lines: every design elsewhere on this page pays a chip-to-chip cost this wafer never has to.

Three more bets: open silicon, in-memory compute, and hard-wired transformers

Where each bet sits: capacity vs bandwidth, flexible vs efficient

1. Toggle the axis: capacity vs bandwidth, or flexibility vs efficiency.
2. Groq's chips: tiny capacity, huge bandwidth — fast, but needs hundreds of chips for a big model.
3. GPUs and TPUs: large off-chip memory, still fast, and far more flexible for arbitrary programs.
4. Cerebras: one wafer gives both high capacity and high bandwidth, at the cost of never leaving that wafer.

What LPULite actually rebuilt — and at what scale

1. Borrowed directly: the names ICU, MEM, VXM, MXM, SXM — straight from Table I of the 2020 paper.
2. Borrowed the idea: a compiler writes the whole schedule in advance; no branches, no loops, no guessing.
3. Not attempted: chip-to-chip scaling (1 FPGA vs up to 10,440 chips) and the lane count (8 vs 320).
4. The team says so themselves — see what's real, partial, and what it isn't and the full comparison.

The whole chip in one drawing — six parts and two roads

1. The ICU holds up to 1,024 instructions and steps through them, one per tick.
2. MEM1 = the model's weights. MEM0 = scratch for results.
3. MXM (8×8 grid of multipliers) does the matrix maths.
4. VXM does row work: normalise, softmax, add, re-squeeze to 8 bits. SXM rearranges rows.
5. Everything travels on two roads: a narrow 8-bit bus and a wide 32-bit bus.
6. An ARM processor outside loads the program, starts it, and reads the answer.

The chip's unit of data: a row — 8 small numbers and 1 shared scale

Two shared roads, and one sender per tick

One instruction = 96 switches that set every unit at once

1. Bits 0–11: who sends and who receives on each road.
2. Bits 12–45: MEM0 and MEM1 read/write and a 15-bit address each.
3. Bits 46–62: MXM — load input or weight, start, clear, which row to output.
4. Bits 63–87: SXM load/emit and VXM mode (ReLU, softmax, norm, residual op).
5. Bits 88–95: reserved. All 96 bits act in the same tick.

The conductor doesn't think: it just counts

One multiply–accumulate cell, with scales that don't match

1. First product: 2 × 1 at scale 2⁻⁴ (real 0.125).
2. Second product: 3 × 1 at scale 2⁻² (real 0.75).
3. Line them up to the finer scale: 3 × 2⁻² = 12 × 2⁻⁴ (shift left 2).
4. Add: 2 + 12 = 14 at scale 2⁻⁴ = 0.875. Correct.

The matrix unit: 64 cells multiplying in the same tick

The clever trick: build W · x out of repeated outer products

1. Goal: y = W · x. Take x[0] and copy it into all 8 lanes (broadcast).
2. Load weight row 0 = the 8 weights that multiply x[0]. Start: row 0 of the grid gains x[0]·W[c][0].
3. Next input x[1], weight row 1, start: row 0 gains x[1]·W[c][1].
4. …after every input, row 0 holds Σ x[k]·W[c][k] = 8 outputs of W·x.
5. Row 0 → wide bus → VXM re-squeezes to 8 bits → MEM0.

SXM doesn't do maths — it turns rows into columns

1. Transpose: the 8 rows loaded in come out as the 8 columns.
2. Broadcast: load one row 8 times → each output row repeats one lane 8 times.

The vector unit: an assembly line that each row rides through

1. A row arrives from the wide bus (Q8.8: value × 256).
2. Switchable stages: bias add, ReLU, ÷2.
3. Branch: softmax (many rows) or straight on. Optional RoPE, RMSNorm, residual.
4. Always last: requantize to 8-bit lanes + scale, then out.

RMSNorm with a 32-entry lookup table instead of a square root

1. Inputs: one row of 1s, one row of 3s (16 values).
2. Sum of squares = 8·1 + 8·9 = 80; mean = 5.
3. No square root: highest bit of 5 is bit 2 → next bits index the table → shift by 1.
4. Multiply: 1 → 114, 3 → 342 (exact: 114.5 and 343.4). One table read, a few shifts.

Softmax needs e^x and division — the chip uses two tables

After the maths, squeeze back to 8 bits — by counting shifts

1. Input in Q8.8: [256, −512, 128, −64] = real [1, −2, 0.5, −0.25].
2. Largest magnitude 512. Shift right until ≤ 127: 3 shifts.
3. Shift every lane: [32, −64, 16, −8].
4. Scale = 3 − 8 = −5. Check: 32 × 2⁻⁵ = 1.0 ✓

Two memories: the model and the scratchpad

Take one real row from the compiled image — what does it actually do?

1. Pick row 31 — the instruction that finally writes the answer back to memory.
2. Hex: w0=0x000220C3, w1=0x06000000, w2=0x00000000 — three 32-bit words, exactly as the ARM writes them over MMIO.
3. Slice the 96 bits into the same fields icu.sv assigns — one coloured block per field, hover any of them.
4. Read off the non-zero fields: westbound_sel=3 (VXM), westbound_consumer_sel=3 (MEM0), mem0_write_en=1, mem0_addr=8.
5. In English: VXM drives the narrow bus, MEM0 listens, and writes row 8 — that's write VXM to MEM0[8], verbatim from the compiler's own trace note.

Ten real ticks: the chip's very first computation, cycle by cycle

A memory read isn't instant — trace the real 2-tick hold

One MAC cell, two different ways to align mismatched scales

1. Switch to inside MXM — the mode the real hardware uses.
2. First product: 2 × 1 at scale 2⁻⁴ (real 0.125).
3. Second product: 3 × 1 at scale 2⁻² (coarser — real 0.75).
4. mxm.sv compares the two scales once and hands every cell the same product_shift: shift the coarser one left 2 → 12 × 2⁻⁴.
5. Add: 2 + 12 = 14 × 2⁻⁴ = 0.875 ✓, saturating at 32 bits (mac.sv:122-127).

64 identical copies of one line: the real generate loop

1. Clear — resets every wght_reg AND every acc_o to zero.
2. Load a random input row and weight row into the ingress registers.
3. Start — all 64 mac instances fire on the SAME tick, hover any cell to see its formula.
4. Start again — the grid is a true ACCUMULATOR, not a snapshot.

Two magic numbers, 5A5 and A5A — and why the board skips them

Five real registers, s0 through s4 — and three 2-to-1 muxes

1. Toggle bias off — mux1 now passes data straight through, unchanged.
2. Bias back on.
3. Toggle ÷2 on — every lane's value is arithmetic-shifted right by 1 in stage 3.
4. Toggle softmax on — stage 4 now routes to the softmax core instead of straight to the quantizer.

Softmax is a 4-state machine — walk it with 4 real scores

Requantizing takes exactly 2 clock edges — proved by the testbench

1. Cycle N: in_valid=1, x_input = the four Q8.8 values.
2. Edge: ingress_data_reg <= x_input (quant.sv:76) — now sitting in a register.
3. Combinationally, THIS cycle: count shifts until the largest magnitude (512) fits under 127 → 3 shifts.
4. Edge: q_row_out <= mux_word, out_valid<=1 — the 8-bit lanes and scale −5 land one tick later.
5. Check by hand: 32 × 2⁻⁵ = 1.0 ✓, −64 × 2⁻⁵ = −2.0 ✓ — exactly what the testbench's $fatal guards asserted.

The bus is two tiny modules: a mux and a decoder

1. Pick MEM0 as the producer on the narrow (westbound) road.
2. Pick MXM as the consumer — this is the everyday "load a weight row" path.
3. Switch producer to VXM instead — same mux, same wires, different select value.
4. Only ONE producer and ONE consumer light up per tick, on each of the two independent roads.

The compiler is a Python program that writes the chip's program

1. MEM1 layout: every tensor's address is just "rows written so far" — sequential, no gaps.
2. The weight re-layout trick: transposed_matvec_rows() repacks W[out][in] as W[input_index][output_block] — input-major, for MXM's outer-product trick.
3. emit() appends one row to instructions[] AND one {pc, note} to trace[] — every instruction in the image has a matching English sentence, if you know where to look.
4. The chip's whole first computation — 32 real instructions — is ONE Python call, unrolled.

What the ARM does 900 instructions at a time, forever

Quartus says the logic tops out at 9.84 MHz — here's the report

1. CLOCK_50 (board) feeds a free-running 3-bit counter.
2. qsys_clk = qsys_clk_div[2] — bit 2 of the counter is an implicit ÷8.
3. TimeQuest's Fmax summary: 9.84 MHz slow-85°C, 9.62 MHz slow-0°C.
4. 58.373 ns of setup slack remains on the real 160 ns (6.25 MHz) tick — comfortably closed, deliberately conservative.
5. Honest gap: the plain-text report only exports the Fmax SUMMARY — it does not name which register pair is the critical path; that lives only in Quartus's HTML report, not checked into this repo.

The model it runs is tiny — on purpose

One transformer layer, coloured by which part of the chip does it

1. Token + position embeddings are added (VXM) and normalised (VXM).
2. MXM computes Q, K, V — three 16→16 matrix multiplies.
3. Attention: K flipped (SXM), scores QKᵀ (MXM), softmax (VXM), weighted V (MXM).
4. Output projection (MXM) + residual add (VXM).
5. MLP: 16→64 (MXM), ReLU (VXM), 64→16 (MXM), add (VXM).
6. LM head 16→27 (MXM) → 27 scores → ARM picks the top character.

The compiler turns a model into 974 rows and 4,920 ticks

1. Train in Python: 4,192 float weights, with 8-bit rounding applied in every forward pass.
2. Pack: blocks of 8 + a scale → 974 rows at fixed addresses in MEM1.
3. Compile: every read, bus choice and start, tick by tick → 4,920 96-bit instructions.
4. Export to a hex image and a C header → the ARM loads it in pages of 900.

Attention, done by ordinary units in sequence

1. From X: Q, K, V (MXM).
2. SXM transposes K → Kᵀ (61 ticks).
3. MXM: Q·Kᵀ = one score per position (120 ticks).
4. ARM: ÷2 and mask the future (−127). VXM: softmax (552 ticks).
5. MXM: weights × V = this head's output (148 ticks). ×4 heads, then VXM merges.

Follow one character through the machine: v → i

Reading the prompt vs writing new letters: every letter is a full pass

What it actually prints: sat → satvik

One board, two brains: an ARM computer and an FPGA

1. The ARM side: Linux, the terminal, the C runtime.
2. The FPGA side: the LPU core built out of programmable blocks.
3. They talk over a bridge: the chip's memories appear as addresses the ARM can read and write.
4. Control address: “run exactly N ticks”, then the ARM polls until it's done.

The design fills the FPGA to the last block

The chip ticks at 6.25 million times a second — because it has to

Where a character's time goes: mostly not the chip

From SystemVerilog to a silicon layout — as a showcase

1. SystemVerilog: the circuit described as code (src/*.sv).
2. Synthesis: turned into standard logic cells from a library.
3. Place & route: cells and 30 SRAM blocks positioned, wires drawn.
4. GDS: the layout file a fab prints. Here: drawn as a showcase, not a routed tape-out.

It printed “sata”, then nonsense — here's what fixed it

1. “sata”: memory was read a tick too early → all scores 0 → token 0 = “a”.
2. random: instruction pages overran and old values survived → different answer each run.
3. consistently wrong: scales mixed up — MAC added 2⁻⁵ and 2⁻⁸ numbers raw; quantizer off by 8; RMSNorm halves.
4. correct: sat → satvik, matching the CPU reference.

How do you know a chip is right? Compare at every level

1. CPU reference: bit-accurate INT8 Python — all 9 names complete.
2. Unit testbenches: each block (MAC, quantizer, softmax, RMSNorm) against worked numbers.
3. Full-chip simulation: the same interface the ARM uses → “sat” gives “v”.
4. Physical board: sat → satvik, and a cycle counter proves the exact tick count.
5. Mismatch? model → schedule → interface → handshake → arithmetic, one level at a time.

What's real, what's partial, what it isn't

Same ideas, wildly different scale

What it would take to run a real 8-billion-weight model

1. LPULite today: 4,192 weights in ~288 KiB of block RAM.
2. An 8B model at INT8: 8 GB — ~27,000× more memory.
3. Even Groq's gen-1 chip (230 MB) needs ~35 chips just for the weights.
4. Plus: a general compiler, an ASIC clock, and the ARM's work moved on-chip.

Where to go from here

Every word, one line each

Nine months, one chain: every month breaks the one before it

Every pick passed the Milen test — scored from its real narration

How to not become someone who knows many names and nothing else

Month 1: how does a switch become a computer?

Month 2: what is a gate made of, and why is it slow and hot?

Month 3: describe hardware in text and put it on a real chip

Month 4: what limits speed, and how do real CPUs go faster?

Months 5–9: from what a model computes to your own accelerator on silicon

NPTEL: not the teacher — the problem sets and the certificate

What to buy, what is free, and when you need it

1. Month 1: free simulators only.
2. Month 2: breadboard kit + multimeter.
3. Month 3: Tang Nano 9K FPGA (+ optional logic analyser).
4. Month 8: optional Tiny Tapeout tile.

Your notebook: every snap, note and highlight

Every tool we plugged in — and what we didn't

Watch and take notes, lying down

Lying down mode: voice, read-aloud & the remote

Logic lab: build it, don't just watch it

Verilog lab: rebuild LPULite, one module at a time

A real Icarus Verilog compiler runs entirely in this tab (WebAssembly) — nothing leaves your browser. Write the module, hit Run grader, read the waveform.

Practice: cards that remember what you forget

Practice gym: every topic, one question at a time